This invention relates to a high-speed serial interface, especially in a programmable integrated circuit device, such as a programmable logic device (PLD), which may operate at different data rates.
It has become common for programmable devices to incorporate high-speed serial interfaces to accommodate high-speed (i.e., greater than 1 Gbps) serial I/O standards.
An early example of such a standard was the XAUI (eXtended Attachment Unit Interface) standard. In accordance with the XAUI standard, for example, a high-speed serial interface includes transceiver groups known as “quads,” each of which includes four transceivers and some central logic.
In one implementation, each transceiver is divided into a physical medium attachment (PMA) portion or module which communicates with outside devices, and a physical coding sublayer (PCS) portion or module which performs serial processing of data, for transmission to, or that is received from, those outside devices.
Even when operating under identical standards, a particular serial interface may operate at different speeds, depending, for example, on line conditions. Thus, it is known for the PCS of a serial interface to negotiate with its counterpart for the highest speed that will support reliable transmission and reception at both ends. Originally, in programmable device implementations, such negotiation was carried out in software or in the programmable logic core of the programmable device, outside of the serial interface itself.
Later serial protocols, such as PCI Express Generation 2 (“PCIe2”), 4 Gbps Fibre Channel (“4GFC”) and 8 Gbps Fibre Channel (“8GFC”), had shorter speed negotiation windows. Those windows generally were too short for relatively slow software or programmable logic. Accordingly, commonly-assigned U.S. Pat. No. 7,684,477 disclosed a high-speed serial interface of the type described, with a built-in hardware module for automatic speed negotiation to select one of two data rates, that could be incorporated into a programmable device.
Newer serial protocols, such as PCI Express Generation 3 (“PCIe Gen 3”) and 40/100 Gigabit Ethernet, may require selection from among three data rates. Moreover, such protocols may require that rate negotiation occur at a fourth, substantially slower, data rate.